As is known in the art, many monolithic microwave integrated circuits (MMICs) having Group III-Nitride semiconductors, sometimes referred to as nitride semiconductors, such as for example, gallium nitride-based (AlGaN/GaN) high electron mobility transistors (HEMTs), are increasingly being used for high-frequency and high-power applications. Group III-Nitride are herein after sometimes also referred to as Group III-N which includes, for example, binaries InN, GaN, AlN, their ternary alloys such as AlxGa1-xN (AlGaN) alloys and other nitrogen based alloys.
In order to realize the potential of these HEMT devices it is necessary to achieve low-resistance, good edge acuity and reliable metal to metal contacts, and metal to semiconductor Ohmic contacts and Schottky contacts (for gate formation). Most Group III-N foundry metal to metal and metal to semiconductor low resistance Ohmic contacts use gold (Au) to reduce sheet resistance (for transmission lines and Ohmic contacts) and to decrease oxidation during the high temperature anneal required to achieve the lowest metal to semiconductor Ohmic contact resistance to active devices. The preferred contact metal for Schottky gate contacts is Nickel, owing to its large work function (≥5 eV),
As is also known, in many Monolithic Microwave Integrated Circuits (MMICs) and other integrated circuits (ICs), electrical connection is made to the bottom of the MMIC for both ground and electrical signals to mounted chips, these connections are made through electrically conductive vias passing through the substrate and/or a semiconductor epitaxial layer on at least a portion of the substrate to electrical contacts that connect the vias to a metallization on the wafer; sometimes referred to as a front-side metallization.
Traditionally, Group III-N HEMT MMICs and devices are fabricated by liftoff-based processing in III-V foundries. Recently, however, Group III-N HEMTs have begun to be fabricated using high yield silicon (Si) like, Au-free, subtractive processing techniques in Si CMOS foundry environments. More particularly, a “lift-off” process is where a mask has a window to expose a selected portion of a surface where a material is to be deposited. The material is deposited onto the mask with a portion of the material passing through the window onto the exposed selected portion of the surface. The mask is lifted off the surface with a solvent along with portion of the material on the mask (the unwanted portion of the deposited material) while leaving the desired portion of the material on the exposed selected portion of the surface. A “subtractive” process is where a material is first deposited over the entire surface. Then a mask is formed to cover only over a selected portion of the deposited material (the portion which is to remain after the processing); the unwanted portions of the deposited material being exposed. An etchant is then brought into contact with the mask thereby removing the exposed unwanted portion while the mask prevents the etchant from removing the covered desired portion of the material.
Relative to Si CMOS foundries, it is well known that the yield and cost of III-V compound semiconductor devices and circuits (processed in traditional III-V foundries) has long been limited by low wafer volumes, increased substrate handling during processing, the widespread use of liftoff-based processing techniques to define metal lines, and the use of time consuming electron beam lithography for sub 500 nm gate lithography. The Si CMOS foundry environment on the other hand has the benefit of high wafer volumes, large wafer diameters (≥200 mm), highly automated cassette to cassette wafer fabrication or processing tools, subtractive processing techniques, advanced optical lithography cluster tools and techniques (capable of defining sub 100 nm features), and the Moore's law paradigm that drives both equipment development and technology node development.
However, as noted previously, to take advantage of the benefits of the Si foundry infrastructure and background Si CMOS wafer volumes, the developed Group III-N processes have to be Au-free. Gold is a deep level trap dopant in Si. Therefore, Au is not allowed in the front end or back end of Si CMOS foundry fabrication lines as it is a serious contamination concern that can cause catastrophic yield problems.
Gold free processing of GaN (or other III-V) device wafers in Si foundry environments therefore requires the use of Si foundry back end of line (BEOL) compatible metallizations such as aluminum (Al) or copper (Cu). Copper is the most attractive of these metals to use as it has superior electrical conductivity and electro-migration resistance. However, because of the lack of volatile copper dry etch byproducts, copper cannot readily be subtractively patterned by the techniques of photolithography wherein photoresist masking and plasma etching have been used with great success with aluminum. To process copper, the Damascene process (which is also subtractive), was developed. In the Cu Damascene process, a host insulator material for the copper, typically an underlying insulating layer (usually silicon dioxide), is patterned with open trenches where the copper is to be formed. A thick coating of copper that significantly overfills the trenches is deposited on the insulating layer, and chemical-mechanical planarization (CMP) is used to remove the excess copper that extends above the top of the insulating layer. Cu filled within the trenches of the insulating layer is not removed and becomes the patterned conductive interconnect.
As is also known in the art, while Cu is manageable, it also poses its own contamination risk for Si foundries. Barrier layers should completely surround all copper interconnections, since diffusion of copper into surrounding materials would degrade their properties. Typically, the trenches are lined with thin tantalum (Ta) and/or tantalum nitride (TaN) metal layers (as part of the Ta/TaN/Cu plating seed metal stack) to act as diffusion barriers along the bottom and sides of the Cu metal interconnects. At post Cu CMP the top of the interconnect metal is coated with SiNx to act as the top interface diffusion barrier, to prevent oxidation during interlayer oxide deposition, and to act as a stop etch layer (during the trench etch of the silicon dioxide) for additional interconnect formation. Additional process complications arise, however, when back to front side metal interconnects are facilitated by through-wafer or through-semiconductor layer vias that require a chlorine—(or other oxidizer) based etches to form these vias. The chloride-based etch by-products are nonvolatile and the etch process results in a degraded Cu interfacial surface.
As is also known in the art, Field Effect Transistors (FETs) used in high frequency applications are typically Group III-V devices, such as Gallium Nitride (GaN) HEMT FETs. While today many of these Gall FETs are fabricated in foundries specifically designed to fabricate these GaN FETs, it would be desirable to also have these devices fabricated in foundries currently designed to fabricate Silicon (Si) devices.